Field programmable device

ABSTRACT

A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at least one pair of outputs; and error detection circuitry for comparing the outputs to determine if there has been a configuration error.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to a field programmable device (FPD) andin particular but not exclusively to Field Programmable Gate Arrays(FPGA).

2. Description of Related Art

Programmable gate arrays (PGA) have dramatically changed the process ofdesigning digital hardware over the last few years. Unlike previousgenerations of digital electronic technology, where board level designsincluded large numbers of integrated circuits containing basic gates,virtually every digital design produced today consists mostly of highdensity integrated circuit devices. This is applied not only to customdevices such as processing units and memory, but also to solid statemachines such as controllers, counters, registers and decoders.

When such circuits are destined for high volume systems, they have beenintegrated into high density gate arrays. However, for prototyping orother low volume situations, many product designs are built using fieldprogrammable devices (FPD), one variant of which are field programmablegate arrays (FPGA). A field programmable device such as the FPGA is atits most basic level a series of configurable logic blocks (CLB),interconnected by a series of configurable connections or links, andread from and written to by a configurable input/output device.

The effectiveness of a field programmable device is the ability of thedevice to represent a required digital design, and be capable of beingaltered without the need for complete replacement. This ability isdependent on several factors such as device speed, and the complexity ofdesign capable of being simulated. The complexity of the design isitself dependent on the complexity of the interconnections between theconfigurable logic blocks, and the number of the configurable logicblocks. The greater the number of blocks and the more complex theinterconnection environment, the more complex the design that can berealized.

Interconnects are generally programmed, in the case of memory basedFPDs, by a series of switching matrices controlled by memory latches.The memory latches create closed or open circuits between pairs ofconducting lines. These configuration latches are supplied configurationdata from a series of configuration registers and are enabled by anaddress register in a manner similar to the addressing and writing to atypical memory cell. The address and configuration data are passed tothe configuration latches by a series of configuration and addresslines.

In order to test that the configuration has been carried outsuccessfully, a verification step is typically introduced afterconfiguration and prior to using the device in an active mode. Thisverification step involves using a series of test input signals, or testvectors, and monitoring the output of the FPD. The output of thesimulated circuit is checked against the test vector input to enable theverification step to determine if a configuration error has occurred andif enough test vectors are entered, the verification step may determinewhich region or which configuration latch has failed.

This verification step therefore increases the time spent in theconfiguration mode. Also should any errors be detected the device has torestart the whole configuration cycle again. Solutions for detecting anerror in data stored in configuration SRAM and user assignable SRAM in aFPGA have been proposed. U.S. Pat. No. 6,237,124 describes such amethod. This method, though, describes separate write and read phases.The write phase describes a method for writing to configuration SRAM andalso using the same data into Cyclic Redundancy Check (CRC) circuitry.The read phase describes when data is read from the configuration SRAMand fed into the same CRC circuitry, then comparing the CRC values todetermine if there is a fault. This method therefore requires two phasesin order to perform a single test. In other words, a write phase isrequired to initiate the test followed by a read phase to trigger thetest value. This test is also unable to determine the exact location ofthe fault.

Based upon the foregoing, there is a need for a field programmabledevice that is efficiently configured and verified.

SUMMARY OF THE INVENTION

Embodiments of the present invention overcome the shortcomings describedabove and satisfy a need for an improved field programmable device thatis efficiently configured and verified.

Embodiments of the present invention at least mitigate the problemsdescribed above.

There is provided, according to embodiments of the invention, a fieldprogrammable device including a plurality of logic blocks; a pluralityof connections connecting the logic blocks; configuration means foroutputting configuration data for programming the device, theconfiguration means providing at least one pair of outputs; and errordetection means for comparing the outputs to determine if there has beena configuration error.

The error detecting means may include means for comparing the outputs.In an embodiment of the present invention, the comparing means may be alogic XNOR gate.

The error detection means may be arranged to determine the presence ofan error if a pair of outputs are determined to be the same. The errordetection means may include at least one transistor arranged to providea predetermined output when an error is determined. The at least onetransistor may be a pull-up transistor.

The device may further comprise at least one pair of outputs comprisinga signal and its logical inverse.

The error detection means may be arranged to determine errors in a firstpart of the device and then determine errors in a second part of thedevice. The error detection means may be arranged to determine errors inthe first part when a clock signal has a first state and determineerrors in the second part when the clock signal has a second state.

One of the first and second parts of the device may include the outputsof the configuration means. One of the first and second parts of thedevice may include the plurality of connections. At least one of thelogic blocks and the connection means may be configurable.

The error detection means may be arranged to determine the location ofan error.

The error detection means may include means for providing an output foreach line of the device. The means for providing an output for each linemay include storage means. The means for providing an output for eachline may include comparing means.

Embodiments of the present invention allow the testing of configurationdata to be carried out at substantially the same time as the act ofconfiguring the device.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention and how the same maybe carried into effect, reference will now be made by way of exampleonly to the accompanying drawings in which:

FIG. 1 shows a schematic view of a field programmable device.

FIG. 2 shows a detailed view of a logic device in the field programmabledevice of FIG. 1.

FIG. 3 shows a view of the interconnections of the configuration anddata paths in the field programmable device of FIG. 1.

FIG. 4 shows a switch matrix element capable of being implemented in thelogic device of FIG. 3.

FIG. 5 shows a flow diagram showing the write/read cycle for a fieldprogrammable device utilizing the switching matrix of FIG. 4.

FIG. 6 shows a switch matrix incorporating an embodiment of the presentinvention and capable of being implemented in the logic device of FIGS.2 and 3.

FIG. 7 shows a flow diagram showing a test method incorporating anembodiment of the present invention.

FIG. 8 shows in further detail the enable generation circuit of FIGS. 4and 6.

DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE PRESENT INVENTION

Reference is now made to FIG. 1, which shows a field programmable device1 within which embodiments of the present invention can be implemented.The Field Programmable Device (FPD) 1 may include a digital logic device7, and a series of pins providing connections to and from the logicdevice. These pins are bi-directional or uni-directional and may bedefined in each specific design. For example, in FIG. 1 pins 3 providedigital signals to the logic device, i.e., inputs. Pins 5 providedigital signals from the logic device, i.e., outputs.

The FPD 1 may be capable of being operated in one of two modes. Thefirst mode is an active mode, whereby the device simulates the action oractions of a digital or a series of digital circuits. The logic device 7may receive inputs via the input pins 3 and provide outputs via theoutput pins 5, whereby these inputs may provide digital data and/or aclock signal.

The second mode is a configuration mode. In this mode, the logic device7 is configured dependent on input data. When configured, the logicdevice 7 is arranged to simulate the action of the required digitalcircuit or circuits. This configuration input data may be passed to thelogic device 7 via the input pins 3 or output pins (acting as inputpins) 5 or by a separate series of configuration pins 2.

With reference to FIG. 2 which shows the FPD 1 in more detail, the logicdevice 7 may include a processing block 110 which comprises the elementsneeded to allow the FPD 1 to simulate the required circuit. In order tocommunicate to devices outside the FPD 1, a series of Input/OutputBlocks (10B) 117 are provided at the edges of the processing block 110.These IOBs 117 are configurable to be capable of buffering signalsreceived from and output to the FPD connection pins 3,5. The IOBs 117are connected to the rest of the processing block 110 by a plurality ofvertical conductive paths (or vertical data lines) 119, and horizontalpaths (or horizontal data lines) 123. These conductive paths run invertical and horizontal directions and substantially span the processingblock 110 of the logic device 7.

These conductive paths 119 and 123 pass through a series of SwitchingMatrices (SM) 115. The intersection of vertical paths 119 and horizontalpaths 123 create short or open circuits, connecting or isolating thepaths 119 and 123 in dependence on the configuration of thecorresponding switching matrix 115. The switching matrix 115 thus allowsa vertical path 119 to be connected to a horizontal path 123, allows ahorizontal path 123 to pass through the switch matrix 115, and/or allowsa vertical path 119 to pass through the switch matrix 115.

These conductive paths, 119 and 123, also pass information and/or datato and from the terminals of the Configurable Logic Blocks (CLB) 121.The arrangement of the Configurable Logic Blocks 121 and switchedmatrices 115 is normally such that no two CLBs 121 are directlyconnected together by a single conductive path 119,123. Therefore,signals from one CLB 121 to another CLB 121 are routed via switchedmatrices 115. An alternate arrangement in some areas of the processingblock 110 allows direct connections between CLBs 121 in somecircumstances.

The CLB 121 may include in a first stage a series of look up tablesoutputting values in dependence on a series of inputs, coupled to asecond stage where the values of these look up tables are logicallycombined or selected in dependence on the configuration of thatparticular CLB 121.

In order to configure both the Switched Matrix 115 and the ConfigurableLogic Block 121, additional circuitry may be required. This circuitry isfeatured in the configuration block 120. The circuitry of theconfiguration block 120 may include a configuration controller 101, aconfiguration data register 125 and address register 103. Theconfiguration controller 101 controls the configuration within the FPD1. The configuration controller 101 receives signals 105 via theconfiguration pins 2. The controller 101 can instruct the addressregisters 103 and configuration data registers 125 via an addressregister conductive path 107 and a configuration register conductivepath 109, respectively. Configuration data, as well as instructions fromthe controller 101, can also be loaded onto the configuration dataregister 125 via the same configuration register conductive path 109.

The configuration data is stored in the configuration data register 125and output to the elements in the processing block 110 on a series ofconfiguration data lines 111. The data is directed to the correct partof the processing block 110 in dependence on the signals output from theaddress register 103 via the address lines 113. These address lines 113and configuration data lines ill intersect the processing block 110,spanning substantially all of the configurable elements in theprocessing block 110 (not shown for clarity purposes).

FIG. 3 shows in more detail a part 130 of the processing block 110.Configurable Logic Blocks 121 are connected to each other via horizontalconductive paths 123 and vertical 119 conductive paths. Connecting pathstogether and routing pathways on these conductive paths, 119 and 123,are the switching matrices 115. The switching matrices 115 are alsoconnected to the configuration data lines 111 and the address lines 113,which run substantially continuously across the processing block 110.

FIG. 4 shows in further detail the circuitry used to configure theswitch matrix 115. A switch matrix 115 may include a plurality ofhorizontal data lines 123, a plurality of vertical data lines 119, aplurality of configuration data lines 425, a plurality of address lines113, a plurality of enable signal generators 419, a plurality ofconfiguration latches 427, a plurality of connecting transistors 450 anda plurality of output switch transistors 435.

The horizontal data lines 123 may pass through the switch matrix 115from one horizontal side to the opposite side (of which one horizontaldata line 123a is shown in FIG. 4).

The vertical data lines 119 may pass through the switch matrix 115 fromone vertical side to the opposite vertical side (of which one verticaldata line 19a is shown in FIG. 4).

The switch matrix configuration data lines 425 may pass through theswitch matrix 115, entering on one side and being connected to theconfiguration data lines 111, and connected on the opposite side to aseries of switch matrix configuration outputs 439.

The address lines 113 may enter the switch matrix 115, and pass alongthe switch matrix 115. The address lines 113 may in some embodiments ofthe present invention pass through the switch matrix 115 and exit theopposite side to continue the path of the address lines 113.Alternatively, with reference to FIG. 3 and FIG. 4, the address lines113 may terminate within the switch matrix 115, with a path external tothe switch matrix 115 connecting to each of the switch matrices 115.

The enable signal generator 419 has a first input connected to the clocksignal line 401, a second input connected to an address signal 113, afirst output connected to an input enable line 421 and a second outputconnected to an output enable line 423.

The configuration latch 427, has a first (data) input 429 connected tothe switch matrix configuration data line 425, a second (enable) input431 connected to the input enable line 421, and an output 433.

The connection transistor 450 has its gate 451 connected to theconfiguration latch output 433, one of its remaining terminals 453connected to one of the vertical data lines 119a and the remainingterminal 455 connected to one of the horizontal data lines 123a.

The output switch 435 has its gate connected to the output enable line423, one of the remaining terminals connected to the output 433 of theconfiguration latch 427, which has its enable input 431 connected to theinput enable line 421 provided from the same enable signal generator 419supplying the output enable line 423 connected to the gate of the outputswitch 435. The remaining terminal of output switch 435 is connected tothe switch matrix configuration data line 425 which is connected to thedata input 429 of the configuration latch 427 of which the output 433 isconnected to the other terminal of output switch 435.

The switched matrix 115 has an array of configuration latches. Eachelement 461 of this array may include a pair of enable lines, inputenable 421 and output enable 423, switch matrix configuration data line439 running horizontally through the element, a configuration latch 427with the enable input connected to the input enable 421, and the datainput 429 connected to the switch matrix configuration data line 425.

The output of the configuration latch 427 is passed to the output switch435 which can pass the output back to the configuration line 425. Theconfiguration latch output 433 is also passed to a connection switch 450which can connect a horizontal data line to a vertical data line.

Each element 461 of the latch array is tiled together so that,vertically aligned elements receive the same input and output enablelines supplied by the column enable signal generator 471. Verticallyaligned tiles also receive the same vertical data line. Horizontallyaligned elements 461 receive the same switch matrix configuration dataline 425, and the same horizontal data line 123.

In a typical field programmable device, the process of configuring iscontrolled from the configuration controller 101. The controller 101controls the address register 103 and configuration data register 125.The configuration data register 125 may include a single column with aplurality of rows. Each row element controls the configuration data fora single configuration data line 111. Each row element may include adata configuration latch 403 and a switch 415.

The data configuration latch 403 may include a data input 405 connectedto the configuration controller by the line or lines 109, an enableinput 407 connected to a clock line 401, a first output 409 and a secondoutput 411. The second output 411 is an inverted form of the firstoutput 409.

The switch 415 may include three terminals, a data input, a data outputand a select input. In FIG. 4, the switch 415 may be an NMOS transistorwhich has its gate functioning as the select input, one of theconduction terminals functioning as the data input, and the otherconduction terminal functioning as the data output. The gate of thetransistor of switch 415 is connected to an inverted clock pulse 415,such as provided by the output of an inverter 413, with the inverter'sinput connected to the clock line 401. The switch data input isconnected to the first output 409 of the data configuration latch 403.The switch data output 417 is connected to a configuration data line111.

FIG. 5 shows the action of configuration and verification in an FPDutilizing the configuration circuitry of FIG. 4. In the first step S1,the clock signal is brought low. This allows, in step S2, theconfiguration latch 403 to be fixed and the configuration registerswitch transistor 415 to close. The data configuration latch output 409is passed to the switch matrix 115 via the ‘closed’ configuration switch415 and the configuration data lines 111.

Step S3 involves selecting one of the columns of elements 461 in aswitch matrix to be written to. This is achieved by the address register103 outputting a high signal on one of the address lines 113.

This assertion of an address line 113, along with the clock signal, ispassed to the enable signal generator 419, which in step S4 switches theselected column enable input 421 high, and its enable output 423 low.

With the column enable input 421 high, the corresponding column ofconfiguration latches 427 selected are now able to be loaded withconfiguration data. This configuration data is also passed through theswitch matrix configuration lines 425. These functions are performed instep S5.

At step S6, the clock signal 401 is brought high.

The act of bringing the clock signal 401 high causes, in step S7, theconfiguration register latch 403 to open and accept new data. Atsubstantially the same time, the configuration register switch 415 isalso opened, isolating the configuration register latch output 409 fromthe configuration data lines 111.

The configuration latch 427 column to be read from is selected byoutputting a high signal on the selected column address line 113. In thecase of reading from the same line, the same column address line 113 iskept high. These functions are shown in step S8.

The selected column enable signal generator 419 now switches the enableinput 421 to low and the enable output 423 to high as shown in step S9.

The switching of the states of the enable input 421 and enable output423 closes the selected column output switch 435 and outputs the valuefrom the output 433 of the configuration latch 427 onto theconfiguration data line 425, which is placed on the switch matrix outputline 439.

As can be seen by such a series of steps, the act of writingconfiguration data and reading configuration data cannot be carried outat the same time. In such a method an additional storage means arerequired to store the original configuration data, store theconfiguration latch data and then perform tests based on the storeddata.

There is also a lack of discrimination in the reading of the data. Datais read from the configuration latch 427, but it is not possible todetermine where the error occurred within the configuration cycle. It istherefore not possible to determine if it is possible to amend theconfiguration design to compensate for the error, and if so how tocompensate for the error.

FIG. 6 shows an embodiment of the invention whereby the FPD 1configuration is tested at the same time as it is written to.Embodiments of the present invention may be an FPD having circuitrysimilar to that described in FIG. 4, but further arranged to use thesecond configuration register latch output 411. The elements of FIG. 6which are the same as in the preceding figures are referenced by thesame reference numbers.

The second outputs 411 of the configuration registers 403 are output asa second plurality of configuration data lines, running parallel to thefirst set of configuration data lines and jointly called theconfiguration data lines 111.

The switch matrix 115 of FIG. 6 may further include a plurality ofsecond configuration data inputs, and switch matrix configuration datalines 503. The switch matrix configuration lines 503 are connected onone side of the switch matrix 115 to the second set of configurationlines ill and on the opposite side are connected to a second set ofoutputs 505.

The embodiment of the present invention of FIG. 6 may further include anerror detection block 543. This may be located in the configurationblock or at the end of the processing block.

The error detection block 543 may be of a single column of row elements591, a pull-up device 521, a pull down device 519, and a first output537. Each row element 591 may include a first test data input 593, asecond test data input 595, an Exclusive-NOR (XNOR) gate 597, atransistor switch 513, an error detection latch 525 and a second seriesof outputs 541.

The first test data input 593 is connected to a switch matrix outputline 439, the second test data input 595 is connected to a second switchmatrix output line 505. Each row 591 of the error detection block 543 isarranged whereby both test data input lines are from the same row ofswitch matrix elements.

Each XNOR gate 597 may include a first input 507 connected to the firsttest data input 593, a second input 509 connected to the second testdata input 595, and an output 511.

Each error detection latch 525 may include a first data input connectedto the first test data input 593, a second enable input connected to theinverted clock signal as supplied by passing the clock signal 401through inverter 575, and an output 541.

Each element transistor switch 513 may include a gate connected to theoutput of the XNOR gate 597, one of the conduction terminals connectedto the common pull-up device 521 and the other conduction terminalconnected to the common pull-down device 519.

The test block output 537 is connected to the top terminal of the pulldown device 519.

The pull-up device 521 and pull-down device 519 are arranged such thatthe pull-up device 521 is much stronger than the pull-down device 519,so that if a single transistor conducts the current from the pull updevice 521 to the test block output 537, the output 537 is pulled up toa high reference voltage 523. Otherwise, the test block output 537remains pulled low.

This circuitry of FIG. 6 now enables the configuration mode to beincorporated into a comprehensive test scheme. This scheme may includefour steps: a scan test, a clock low test, a clock high test and anadditional error location test.

Referring to FIG. 7, the first step S101, the scan test, may includeemploying a scan of the chip. A scan is a method of detecting hardwareerrors by passing a series of test signals into the input of the circuitand monitoring a series of nodes in the FPD. This is carried out priorto the configuration mode and can be used to test for faults in inputcircuitry to the configuration data registers, the address registers andany input/output registers. Step S101 may be a boundary scan test thattests the input/output (I/O) connections and I/O circuitry of the FPD.

The second step S102, is taken during configuration when the clocksignal 401 is low. During this step, the configuration data registers125 output the values Q onto the configuration data lines 111 and theinverted value /Q onto the second set of configuration data lines 111.The values Q are loaded into the selected configuration latches 427, andare also passed as the first inputs 593 into the error detection block543. The second input 595 into the error detection block 540 receivesthe inverted values /Q of configuration data registers 125. If these twoinputs 593,595 of each row element 591 are the same an error hasoccurred. The expected inputs 593,595 of each row element 591 should beQ and /Q of the corresponding data configuration latch 403,respectively, but in order that the values are the same, one of thevalues has been corrupted and is wrong. This fault can be detected bythe corresponding XNOR gate 597, which produces a high output when bothinputs are the same. When the output of an XNOR gate 597 goes high, thecorresponding switch transistor 513 is closed connecting the pull-up 521device and pull-down device 519. As the pull-up device 521 is strongerthan the pull-down device 519, the error detection block output 537 isbrought high, indicating an error. This test is aimed at detectingstuck-at faults associated with configuration lines 111 and/or dataconfiguration latches 403.

A stuck-at fault occurs when a tested node is connected to a voltagelevel due to some fault in the circuit. It is therefore incapable ofchanging its voltage level. The fault is that the node is stuck at thevoltage level independent of the expected voltage.

The third step S103 occurs when the clock signal 401 is high. Duringthis step, the configuration register output Q from each dataconfiguration latch 403 is isolated from the configuration data line 111by the corresponding configuration register switch 415. Instead, theoutput of the selected configuration latch 427 is output onto the switchmatrix configuration data line 425 via the corresponding switch matrixswitch 435. Thus the error detection block 7 first input 593 is theoutput of the selected configuration latch 427. The error detectionblock 543 second input 595 is the inverted output /Q of the dataconfiguration register latch 403.

As in the previous step, if the two inputs 593,595 of a row 591 of errordetection block 543 are the same, the corresponding XNOR gate 597activates the corresponding transistor switch 513, which connects thepull-up and pull-down devices, thereby bringing the error detectionblock output 537 high and indicating an error. This test is aimed atdetecting faults within the configuration latch.

These two steps S102, S103 are repeated until either theconfiguration/testing routine is complete or the error detection blockoutput 537 indicates an error has been found. If an error is detected,the output 541 of the error detection block latches 525 can be used andcompared against the original configuration data to determine the exactlocation of the fault. In a further embodiment of the present invention,the outputs 511 of the XNOR gates 597 are used to locate the faultrather than use the error detection block latch outputs 537.

After detection and location of a fault, resolution methods may beemployed to reject the FPD or to compensate for the fault withoutrejection of the whole FPD.

Therefore, embodiments of the present invention describe a method fortesting to be carried out at the same time as configuration.

FIG. 8 shows the enable generation circuitry 419. The enable generationcircuitry 419 may include a clock input connected to clock line 401, anenable input connected to the address line 113, a first logic AND gate602, a second logic AND gate 603, a logic inverter gate 601, an enableinput output 421 and an enable output output 423. The first logic AND602 gate may include a first input connected to the clock input and asecond input connected to the enable input and an output connected tothe enable input output 421. The second logic AND gate 603 may include afirst input connected to an inverted clock input as provided by logicinverter gate 601, a second input connected to the enable input, and anoutput connected to the enable output output 423.

In operation, the enable generation circuit 419 outputs operate to passthe clock signed 401 and its logical inversion only when selected by theaddress register. When the circuit 419 is selected by enable signed 413being in a logic high state, the two outputs of enable generationcircuit 419 are opposite to each other, with each output value dependenton the value of the clock signal 401.

The embodiments of the present invention described above feature theadvantages of being able to write configuration data at practically thesame time as testing the configuration cycle. The embodiments of thepresent invention also feature the ability to locate and potentiallyremedy any error in the configuration cycle.

Embodiments of the present invention may be applied not only toconfiguration elements in a switch matrix but also to configurationelements in other parts of a FPD which contain configurable elements.

Although exemplary embodiments of the method and apparatus of thepresent invention have been illustrated in the accompanying Drawings anddescribed in the foregoing Detailed Description, it is understood thatthe invention is not limited to the embodiments disclosed, but iscapable of numerous rearrangements, modifications, and substitutionswithout departing from the spirit of the invention as set forth anddefined by the following claims.

1. A field programmable device comprising: a plurality of logic blocks;a plurality of connections connecting said logic blocks wherein each rowof logic blocks is connected by a pair of connections spanning the rowof logic blocks; configuration means for outputting configuration datafor programming said field programmable device, said configuration meansproviding at least one pair of outputs coupled to each pair ofconnections; and error detection means for comparing data on said pairof connections during configuration means outputting of theconfiguration data to determine if there has been a configuration error.2. A The device as claimed recited in claim 1, wherein said pair ofconnections comprises a first connection that is input and outputcoupled to a switching matrix configuration latch and a secondconnection bypassing each configuration latch, and wherein said errordetection means comprises means for comparing data on said firstconnection driven by configuration latch state to data on said secondconnection.
 3. A The device as claimed recited in claim 2, wherein saidcomparing means comprises a logic XNOR gate.
 4. A The device as claimedrecited in claim 1, wherein said error detection means are arranged todetermine the presence of an error if data on a pair of connections aredetermined to be the same.
 5. A The device as claimed recited in claim1, wherein said error detection means comprises at least one transistorarranged to provide a predetermined output when an error is determined.6. A The device as claimed recited in claim 5, wherein said at least onetransistor comprises a pull-up transistor.
 7. A The device as claimedrecited in claim 1, wherein said at least one pair of outputs comprise asignal and its inverse.
 8. A The device as claimed recited in claim 1,wherein said error detection means is arranged to determine errors in afirst part of said device and then to determine errors on a second partof said device.
 9. A The device as claimed recited in claim 8, whereinsaid error detection means is arranged to determine errors in the firstpart when a clock signal to the device has a first state and todetermine errors in the second part when the clock signal has a secondstate.
 10. A The device as claimed recited in claim 9, wherein one ofsaid first and second parts of said device comprises the outputs of saidconfiguration means.
 11. A The device as claimed recited in claim 9,wherein one of said first and second parts of said device comprises saidplurality of connections.
 12. A The device as claimed recited in claim1, wherein at least one of said logic blocks and said plurality ofconnections are configurable.
 13. A The device as claimed recited inclaim 1, wherein said error detection means is arranged to determine thelocation of an error.
 14. A The device as claimed recited in claim 13,wherein said error detection means comprises means for providing anoutput for each row of said device.
 15. A The device as claimed recitedin claim 14, wherein said means for providing an output for each rowcomprise storage means.
 16. A The device as claimed recited in claim 15,wherein said means for providing an output for each row compares said atleast one pair of outputs.
 17. A field programmable device comprising: aplurality of logic blocks; at least one switching matrix for controllingconnections between the logic blocks; configuration circuitry coupled tothe at least one switching matrix, for configuring the at least oneswitching matrix, said configuration circuitry providing at least onepair of outputs spanning each row of the plurality of logic blocks, atleast a first output of the pair of outputs used in configuring a latchof the switching matrix along the row, and for connection to an outputof the latch of the switching matrix; and test circuitry coupled tocompare the at least one pair of outputs of the configuration circuitryfor testing the field programmable logic device during the time theswitching matrix is being configured to control the connections betweenthe logic blocks.
 18. The field programmable logic device of as recitedin claim 17, wherein: the at least one switching matrix comprises atleast one storage element having an output that controls whether twodata lines in the at least one switching matrix are connected together;the configuration circuitry comprises at least one configurationregister element having at least one configuration output coupled to atleast one input of the at least one switching matrix; and the testcircuitry compares the output of the at least one storage element andthe at least one configuration output and generates a test output signalhaving a value indicative of a configuration error.
 19. The fieldprogrammable logic device of as recited in claim 17, wherein: the atleast one switching matrix comprises a plurality of storage elements,each storage element having an output that controls whether two datalines in the at least one switching matrix are to be connected together;the configuration circuitry comprises a plurality of configurationregister elements, each configuration register element having aconfiguration output coupled to an input of the at least one switchingmatrix; and the test circuitry compares the output of the storageelements and the configuration outputs and generates a test outputsignal having a value indicative of a configuration error.
 20. The fieldprogrammable logic device of as recited in claim 19, wherein the testcircuitry comprises a plurality of exclusive OR/NOR logic gates, anoutput of each of the exclusive ORTSTOR logic gates capable of pullingthe test output signal to a voltage representative of a predeterminedlogic level indicative of a configuration error.
 21. The fieldprogrammable logic device of as recited in claim 20, wherein the testcircuitry further comprises a plurality of transistors, each transistorhaving a control terminal coupled to the output of a distinct exclusiveOR/NOR logic gate and a conduction terminal coupled to the test outputsignal.
 22. The field programmable logic device of as recited in claim19, wherein the test circuitry further comprises a plurality of storagecomponents, each storage component having a data input coupled to aninput of a distinct exclusive OR/NOR logic gate and a data output. 23.The field programmable logic device of as recited in claim 17, wherein:the at least one switching matrix comprises at least one storage elementhaving an output for controlling whether two data lines in the at leastone switching matrix are connected together; the configuration circuitrycomprises at least one configuration output coupled to at least oneinput of the at least one switching matrix; and the test circuitrycompares the at least one configuration output with the output of the atleast one storage element and generates a test output signal having avalue indicative of a configuration error.
 24. A field programmabledevice comprising: a first block comprising a plurality of logic blocks,and a plurality of connections connecting said blocks; configurationmeans for outputting configuration data for programming said device,wherein said configuration means provides at least one pair of outputs,a first output of said one pair of outputs is output onto one of a firstset of configuration data lines, and a second output of said one pair ofoutputs is output onto one of a second set of configuration data lines,said configuration data lines spanning said first block; and errordetection means connected to an output of said one of said first set ofconfiguration data lines, and to an output of said one of said secondset of configuration data lines, said one of said first set and said oneof said second set being from the same row, said error detection meansarranged to compare said configuration data line outputs from the samerow to determine if there has been a configuration error.
 25. A Thedevice as claimed recited in claim 24, wherein said first set of dataconfiguration lines is input and output coupled to a switching matrixconfiguration latch and said second set of data configuration linesbypasses each configuration latch, and wherein said error detectionmeans comprises means for comparing data on said first set of dataconfiguration lines driven by configuration latch state to data on saidsecond set of data configuration lines.
 26. A The device as claimedrecited in claim 25, wherein said comparing means comprises a logic XNORgate.
 27. A The device as claimed recited in claim 24, wherein saiderror detection means are arranged to determine the presence of an errorif a pair of outputs are determined to be the same.
 28. A The device asclaimed recited in claim 24, wherein said error detection meanscomprises at least one transistor arranged to provide a predeterminedoutput when an error is determined.
 29. A The device as claimed recitedin claim 28, wherein said at least one transistor comprises a pull-uptransistor.
 30. A The device as claimed recited in claim 24, whereinsaid at least one pair of outputs comprise a signal and its inverse. 31.A The device as claimed recited in claim 24, wherein said errordetection means is arranged to determine errors in a first part of saiddevice and then to determine errors on a second part of said device. 32.A The device as claimed recited in claim 31, wherein said errordetection means is arranged to determine errors in the first part when aclock signal to the device has a first state and to determine errors inthe second part when the clock signal has a second state.
 33. A Thedevice as claimed recited in claim 32, wherein one of said first andsecond parts of said device comprises the outputs of said configurationmeans.
 34. A The device as claimed recited in claim 32, wherein one ofsaid first and second parts of said device comprises said plurality ofconnections.
 35. A The device as claimed recited in claim 24, wherein atleast one of said logic blocks and said plurality of connection meansare configurable.
 36. A The device as claimed recited in claim 24,wherein said error detection means is arranged to determine the locationof an error.
 37. A The device as claimed recited in claim 36, whereinsaid error detection means comprises means for providing an output foreach row of said device.
 38. A The device as claimed recited in claim37, wherein said means for providing an output for each row comprisestorage means.
 39. A The device as claimed recited in claim 38, whereinsaid means for providing an output for each row compares said at leastone pair of outputs.
 40. A field programmable device comprising: aplurality of logic blocks; a plurality of connections connecting saidblocks wherein each row of logic blocks is connected by a pair ofconnections spanning the row of logic blocks; configuration circuitryfor outputting configuration data for programming said device, saidconfiguration circuitry providing at least one pair of outputs coupledto each pair of connections; and error detection circuitry for comparingdata on said pair of connections during configuration to determine ifthere has been a configuration error.
 41. A field programmable devicecomprising: a first block comprising a plurality of logic blocks, and aplurality of connections connecting said blocks; configuration circuitryfor outputting configuration data for programming said device, whereinsaid configuration circuitry provides at least one pair of outputs, afirst output of said one pair of outputs is output onto one of a firstset of configuration data lines, and a second output of said one pair ofoutputs is output onto one of a second set of configuration data lines,said configuration data lines spanning said first block; and errordetection circuitry connected to an output of said one of said first setof configuration data lines, and to an output of said one of said secondset of configuration data lines, said one of said first set and said oneof said second set being from the same row, said error detectioncircuitry being arranged to compare said configuration data line outputsfrom the same row to determine if there has been a configuration error.42. A method comprising: programming a field programmable device;outputting, from configuration registers, configuration data used in theprogramming of the field programmable device; and comparing saidconfiguration data during said outputting of configuration data todetermine if there has been a configuration error.
 43. The method asrecited in claim 42, wherein said configuration data comprises at leasta first value and a second value.
 44. The method as recited in claim 43,further comprising determining that there has been a configuration errorif said first value is the same as said second value.
 45. A methodcomprising: receiving both a first configuration data input and a secondconfiguration data input for use in programming a field programmabledevice; loading said first and second configuration data inputs into oneor more configuration latches and into an error detection block; anddetermining, via the error detection block, that an error has occurredif said first and second configuration data inputs are the same.
 46. Themethod as recited in claim 45, wherein said loading said first andsecond configuration data inputs into one or more configuration latchesand into an error detection block occur at least partially concurrently.47. A field programmable device comprising: configuration means foroutputting configuration data for use in programming said fieldprogrammable device, wherein said configuration means provides at leastone pair of outputs; and error detection means for comparing said atleast one pair of outputs during said configuration means outputting ofthe configuration data to determine if there has been a configurationerror.
 48. The device as recited in claim 47, wherein said errordetection means is configured to determine the presence of an error ifdata on a pair of connections are determined to be the same.
 49. Thedevice as recited in claim 47, wherein said error detection meanscomprises at least one transistor configured to provide a predeterminedoutput when an error is determined.
 50. The device as recited in claim49, wherein said at least one transistor comprises a pull-up transistor.51. The device as recited in claim 47, wherein said at least one pair ofoutputs comprise a signal and its inverse.
 52. The device as recited inclaim 47, wherein said error detection means is configured to determineerrors in a first part of said device and then to determine errors on asecond part of said device.
 53. The device as recited in claim 52,wherein said error detection means is configured to determine errors inthe first part of said device when a clock signal to said device has afirst state and to determine errors in the second part of said devicewhen said clock signal has a second state.
 54. The device as recited inclaim 53, wherein one of said first and second parts of said devicecomprises the outputs of said configuration means.
 55. The device asrecited in claim 53, wherein one of said first and second parts of saiddevice comprises a plurality of connections coupled to said device. 56.The device as recited in claim 47, wherein said error detection means isconfigured to determine the location of an error.